Icarus Verilog
Icarus Verilog is a Verilog compiler that generates a variety of engineering formats, including simulation. It strives to be true to the IEEE-1364 standard.
- Developed at electronics
- Sources inherited from project openSUSE:Factory
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Source Files
| Filename | Size | Changed |
|---|---|---|
| iverilog.changes | 0000003411 3.33 KB | |
| iverilog.spec | 0000002150 2.1 KB | |
| verilog-0.9.7.tar.gz | 0001238088 1.18 MB |
Revision 4 (latest revision is 9)
Stephan Kulow (coolo)
accepted
request 222248
from
Dmitry Roshchin (Dmitry_R)
(revision 4)
- Update to version 0.9.7 * no changelog available * removed obsolete iverilog-0.9.6-fix-licensing-issues.patch (forwarded request 222246 from Dmitry_R)
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