Icarus Verilog
Icarus Verilog is a Verilog compiler that generates a variety of engineering formats, including simulation. It strives to be true to the IEEE-1364 standard.
- Developed at electronics
- Sources inherited from project openSUSE:Factory
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Source Files
| Filename | Size | Changed |
|---|---|---|
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Fix-makefile-rules-for-header-files-generated-by-b |
0000001951 1.91 KB | |
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fix-cfparse-include-order-causing-lto-type-mismatc |
0000001635 1.6 KB | |
| iverilog.changes | 0000004273 4.17 KB | |
| iverilog.spec | 0000002720 2.66 KB | |
| verilog-10.2.tar.gz | 0001695227 1.62 MB |
Revision 7 (latest revision is 9)
Dominique Leuenberger (dimstar_suse)
accepted
request 719298
from
Stefan Brüns (StefanBruens)
(revision 7)
Comments 0