File u_sync-pci-ids-with-Mesa-21.2.4.patch of Package xorg-x11-server.32027

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File u_sync-pci-ids-with-Mesa-21.2.4.patch of Package xorg-x11-server.32027

diff --git a/hw/xfree86/dri2/pci_ids/i965_pci_ids.h b/hw/xfree86/dri2/pci_ids/i965_pci_ids.h
index c4072e2ee..646df447b 100644
--- a/hw/xfree86/dri2/pci_ids/i965_pci_ids.h
+++ b/hw/xfree86/dri2/pci_ids/i965_pci_ids.h
@@ -239,14 +239,3 @@ CHIPSET(0x4500, ehl_4x8, "Intel(R) HD Graphics (Elkhart Lake 4x8)")
 CHIPSET(0x4571, ehl_4x8, "Intel(R) HD Graphics (Elkhart Lake 4x8)")
 CHIPSET(0x4551, ehl_4x4, "Intel(R) HD Graphics (Elkhart Lake 4x4)")
 CHIPSET(0x4541, ehl_2x4, "Intel(R) HD Graphics (Elkhart Lake 2x4)")
-CHIPSET(0x9A40, tgl_1x6x16, "Intel(R) HD Graphics (Tigerlake 1x6x16 GT2)")
-CHIPSET(0x9A49, tgl_1x6x16, "Intel(R) HD Graphics (Tigerlake 1x6x16 GT2)")
-CHIPSET(0x9A59, tgl_1x6x16, "Intel(R) HD Graphics (Tigerlake 1x6x16 GT2)")
-CHIPSET(0x9A60, tgl_1x2x16, "Intel(R) HD Graphics (Tigerlake 1x2x16 GT1)")
-CHIPSET(0x9A68, tgl_1x2x16, "Intel(R) HD Graphics (Tigerlake 1x2x16 GT1)")
-CHIPSET(0x9A70, tgl_1x2x16, "Intel(R) HD Graphics (Tigerlake 1x2x16 GT1)")
-CHIPSET(0x9A78, tgl_1x2x16, "Intel(R) HD Graphics (Tigerlake 1x2x16 GT1)")
-CHIPSET(0x9AC0, tgl_1x2x16, "Intel(R) HD Graphics (Tigerlake 1x2x16 GT2)")
-CHIPSET(0x9AC9, tg1_1x2x16, "Intel(R) HD Graphics (Tigerlake 1x2x16 GT2)")
-CHIPSET(0x9AD9, tgl_1x2x16, "Intel(R) HD Graphics (Tigerlake 1x2x16 GT2)")
-CHIPSET(0x9AF8, tgl_1x2x16, "Intel(R) HD Graphics (Tigerlake 1X2X16 GT2)")
diff --git a/hw/xfree86/dri2/pci_ids/iris_pci_ids.h b/hw/xfree86/dri2/pci_ids/iris_pci_ids.h
new file mode 100644
index 000000000..1e8c433b4
--- /dev/null
+++ b/hw/xfree86/dri2/pci_ids/iris_pci_ids.h
@@ -0,0 +1,52 @@
+CHIPSET(0x4c8a, rkl_gt1, "RKL GT1", "Intel(R) Graphics")
+CHIPSET(0x4c8b, rkl_gt1, "RKL GT1", "Intel(R) Graphics")
+CHIPSET(0x4c8c, rkl_gt05, "RKL GT0.5", "Intel(R) Graphics")
+CHIPSET(0x4c90, rkl_gt1, "RKL GT1", "Intel(R) Graphics")
+CHIPSET(0x4c9a, rkl_gt1, "RKL GT1", "Intel(R) Graphics")
+
+CHIPSET(0x4680, adl_gt1, "ADL-S GT1", "Intel(R) Graphics")
+CHIPSET(0x4681, adl_gt1, "ADL-S GT1", "Intel(R) Graphics")
+CHIPSET(0x4682, adl_gt1, "ADL-S GT1", "Intel(R) Graphics")
+CHIPSET(0x4683, adl_gt05, "ADL-S GT0.5", "Intel(R) Graphics")
+CHIPSET(0x4688, adl_gt1, "ADL-S GT1", "Intel(R) Graphics")
+CHIPSET(0x4689, adl_gt1, "ADL-S GT1", "Intel(R) Graphics")
+CHIPSET(0x4690, adl_gt1, "ADL-S GT1", "Intel(R) Graphics")
+CHIPSET(0x4691, adl_gt1, "ADL-S GT1", "Intel(R) Graphics")
+CHIPSET(0x4692, adl_gt1, "ADL-S GT1", "Intel(R) Graphics")
+CHIPSET(0x4693, adl_gt05, "ADL-S GT0.5", "Intel(R) Graphics")
+CHIPSET(0x4698, adl_gt1, "ADL-S GT1", "Intel(R) Graphics")
+CHIPSET(0x4699, adl_gt1, "ADL-S GT1", "Intel(R) Graphics")
+
+CHIPSET(0x4626, adl_gt2, "ADL GT2", "Intel(R) Graphics")
+CHIPSET(0x4628, adl_gt2, "ADL GT2", "Intel(R) Graphics")
+CHIPSET(0x462a, adl_gt2, "ADL GT2", "Intel(R) Graphics")
+CHIPSET(0x46a0, adl_gt2, "ADL GT2", "Intel(R) Graphics")
+CHIPSET(0x46a1, adl_gt2, "ADL GT2", "Intel(R) Graphics")
+CHIPSET(0x46a2, adl_gt2, "ADL GT2", "Intel(R) Graphics")
+CHIPSET(0x46a3, adl_gt2, "ADL GT2", "Intel(R) Graphics")
+CHIPSET(0x46a6, adl_gt2, "ADL GT2", "Intel(R) Graphics")
+CHIPSET(0x46a8, adl_gt2, "ADL GT2", "Intel(R) Graphics")
+CHIPSET(0x46aa, adl_gt2, "ADL GT2", "Intel(R) Graphics")
+CHIPSET(0x46b0, adl_gt2, "ADL GT2", "Intel(R) Graphics")
+CHIPSET(0x46b1, adl_gt2, "ADL GT2", "Intel(R) Graphics")
+CHIPSET(0x46b2, adl_gt2, "ADL GT2", "Intel(R) Graphics")
+CHIPSET(0x46b3, adl_gt2, "ADL GT2", "Intel(R) Graphics")
+CHIPSET(0x46c0, adl_gt2, "ADL GT2", "Intel(R) Graphics")
+CHIPSET(0x46c1, adl_gt2, "ADL GT2", "Intel(R) Graphics")
+CHIPSET(0x46c2, adl_gt2, "ADL GT2", "Intel(R) Graphics")
+CHIPSET(0x46c3, adl_gt2, "ADL GT2", "Intel(R) Graphics")
+
+CHIPSET(0x9A40, tgl_gt2, "TGL GT2", "Intel(R) Xe Graphics")
+CHIPSET(0x9A49, tgl_gt2, "TGL GT2", "Intel(R) Xe Graphics")
+CHIPSET(0x9A59, tgl_gt2, "TGL GT2", "Intel(R) Graphics")
+CHIPSET(0x9A60, tgl_gt1, "TGL GT1", "Intel(R) UHD Graphics")
+CHIPSET(0x9A68, tgl_gt1, "TGL GT1", "Intel(R) UHD Graphics")
+CHIPSET(0x9A70, tgl_gt1, "TGL GT1", "Intel(R) UHD Graphics")
+CHIPSET(0x9A78, tgl_gt2, "TGL GT2", "Intel(R) UHD Graphics")
+CHIPSET(0x9AC0, tgl_gt2, "TGL GT2", "Intel(R) UHD Graphics")
+CHIPSET(0x9AC9, tgl_gt2, "TGL GT2", "Intel(R) UHD Graphics")
+CHIPSET(0x9AD9, tgl_gt2, "TGL GT2", "Intel(R) UHD Graphics")
+CHIPSET(0x9AF8, tgl_gt2, "TGL GT2", "Intel(R) UHD Graphics")
+
+/* Disabled for now until kernel support is ready */
+/* CHIPSET(0x4905, dg1, "DG1 GT2", "Intel(R) Graphics") */
diff --git a/hw/xfree86/dri2/pci_ids/pci_id_driver_map.h b/hw/xfree86/dri2/pci_ids/pci_id_driver_map.h
index 04f372279..5fcd76aac 100644
--- a/hw/xfree86/dri2/pci_ids/pci_id_driver_map.h
+++ b/hw/xfree86/dri2/pci_ids/pci_id_driver_map.h
@@ -19,6 +19,12 @@ static const int i965_chip_ids[] = {
 #undef CHIPSET
 };
 
+static const int iris_chip_ids[] = {
+#define CHIPSET(chip, family, name, desc) chip,
+#include "pci_ids/iris_pci_ids.h"
+#undef CHIPSET
+};
+
 #ifndef DRIVER_MAP_GALLIUM_ONLY
 static const int r100_chip_ids[] = {
 #define CHIPSET(chip, name, family) chip,
@@ -65,6 +71,7 @@ static const struct {
 } driver_map[] = {
    { 0x8086, "i915", i915_chip_ids, ARRAY_SIZE(i915_chip_ids) },
    { 0x8086, "i965", i965_chip_ids, ARRAY_SIZE(i965_chip_ids) },
+   { 0x8086, "iris", iris_chip_ids, ARRAY_SIZE(iris_chip_ids) },
    { 0x8086, "i965", NULL, -1 },
 #ifndef DRIVER_MAP_GALLIUM_ONLY
    { 0x1002, "radeon", r100_chip_ids, ARRAY_SIZE(r100_chip_ids) },

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File u_sync-pci-ids-with-Mesa-21.2.4.patch of Package xorg-x11-server.32027

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