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openSUSE:Leap:15.5:Update
xen.8389
xsa269.patch
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File xsa269.patch of Package xen.8389
x86/vtx: Fix the checking for unknown/invalid MSR_DEBUGCTL bits The VPMU_MODE_OFF early-exit in vpmu_do_wrmsr() introduced by c/s 11fe998e56 bypasses all reserved bit checking in the general case. As a result, a guest can enable BTS when it shouldn't be permitted to, and lock up the entire host. With vPMU active (not a security supported configuration, but useful for debugging), the reserved bit checking in broken, caused by the original BTS changeset 1a8aa75ed. From a correctness standpoint, it is not possible to have two different pieces of code responsible for different parts of value checking, if there isn't an accumulation of bits which have been checked. A practical upshot of this is that a guest can set any value it wishes (usually resulting in a vmentry failure for bad guest state). Therefore, fix this by implementing all the reserved bit checking in the main MSR_DEBUGCTL block, and removing all handling of DEBUGCTL from the vPMU MSR logic. This is XSA-269 Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com> Reviewed-by: Jan Beulich <jbeulich@suse.com> --- a/xen/arch/x86/cpu/vpmu_intel.c +++ b/xen/arch/x86/cpu/vpmu_intel.c @@ -533,27 +533,7 @@ static int core2_vpmu_do_wrmsr(unsigned uint64_t *enabled_cntrs; if ( !core2_vpmu_msr_common_check(msr, &type, &index) ) - { - /* Special handling for BTS */ - if ( msr == MSR_IA32_DEBUGCTLMSR ) - { - supported |= IA32_DEBUGCTLMSR_TR | IA32_DEBUGCTLMSR_BTS | - IA32_DEBUGCTLMSR_BTINT; - - if ( cpu_has(¤t_cpu_data, X86_FEATURE_DSCPL) ) - supported |= IA32_DEBUGCTLMSR_BTS_OFF_OS | - IA32_DEBUGCTLMSR_BTS_OFF_USR; - if ( !(msr_content & ~supported) && - vpmu_is_set(vpmu, VPMU_CPU_HAS_BTS) ) - return 0; - if ( (msr_content & supported) && - !vpmu_is_set(vpmu, VPMU_CPU_HAS_BTS) ) - printk(XENLOG_G_WARNING - "%pv: Debug Store unsupported on this CPU\n", - current); - } return -EINVAL; - } ASSERT(!supported); --- a/xen/arch/x86/hvm/vmx/vmx.c +++ b/xen/arch/x86/hvm/vmx/vmx.c @@ -3099,11 +3099,14 @@ void vmx_vlapic_msr_changed(struct vcpu static int vmx_msr_write_intercept(unsigned int msr, uint64_t msr_content) { struct vcpu *v = current; + const struct cpuid_policy *cp = v->domain->arch.cpuid; HVM_DBG_LOG(DBG_LEVEL_MSR, "ecx=%#x, msr_value=%#"PRIx64, msr, msr_content); switch ( msr ) { + uint64_t rsvd; + case MSR_IA32_SYSENTER_CS: __vmwrite(GUEST_SYSENTER_CS, msr_content); break; @@ -3118,17 +3121,27 @@ static int vmx_msr_write_intercept(unsig __vmwrite(GUEST_SYSENTER_EIP, msr_content); break; case MSR_IA32_DEBUGCTLMSR: { - uint64_t supported = IA32_DEBUGCTLMSR_LBR | IA32_DEBUGCTLMSR_BTF; - if ( boot_cpu_has(X86_FEATURE_RTM) ) - supported |= IA32_DEBUGCTLMSR_RTM; - if ( msr_content & ~supported ) + rsvd = ~(IA32_DEBUGCTLMSR_LBR | IA32_DEBUGCTLMSR_BTF); + + /* TODO: Wire vPMU settings properly through the CPUID policy */ + if ( vpmu_is_set(vcpu_vpmu(v), VPMU_CPU_HAS_BTS) ) { - /* Perhaps some other bits are supported in vpmu. */ - if ( vpmu_do_wrmsr(msr, msr_content, supported) ) - break; + rsvd &= ~(IA32_DEBUGCTLMSR_TR | IA32_DEBUGCTLMSR_BTS | + IA32_DEBUGCTLMSR_BTINT); + + if ( cpu_has(¤t_cpu_data, X86_FEATURE_DSCPL) ) + rsvd &= ~(IA32_DEBUGCTLMSR_BTS_OFF_OS | + IA32_DEBUGCTLMSR_BTS_OFF_USR); } + if ( cp->feat.rtm ) + rsvd &= ~IA32_DEBUGCTLMSR_RTM; + + if ( msr_content & rsvd ) + goto gp_fault; + + /* * When a guest first enables LBR, arrange to save and restore the LBR * MSRs and allow the guest direct access.
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