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File libcpuid.changes of Package libcpuid
------------------------------------------------------------------- Wed Nov 1 20:53:39 UTC 2023 - Jan Engelhardt <jengelh@inai.de> - Update to release 0.6.4 * Support for AMD Genoa, Phoenix, Dragon Range, Ryzen Z1 * Support for Intel Sapphire Rapids-WS, Skylake (server), Cascade Lake, Ice-Lake (server), Sapphire Rapids-SP, Raptor Lake-H/HX, Apollo lake * Improve support for Arrandale, Alder-Lake and Raptor-Lake P/U * Initial support for Centaur CPUs (VIA and Zhaoxin) ------------------------------------------------------------------- Tue Apr 25 11:29:39 UTC 2023 - Martin Pluskal <mpluskal@suse.com> - Update to version 0.6.3: * Support for Intel Pentium and Celeron for Alder Lake-S * Support for Intel Alder Lake-HX * Support for Intel Alder Lake-X * Fix detection of Intel Alder Lake-P * Fix infinite loop in set_cpu_affinity() on macOS * Fix a misprint of extended CPUID in cpuid_basic_identify() * Restore previous thread CPU affinity before returning from cpuid_get_all_raw_data() (#184) * Query CPU info at least once even if set_cpu_affinity() fails * Support for AMD 19h family MSRs * Fix detection of Intel Core i5 Lynnfield * Rename set_error() to cpuid_set_error() and get_error() to cpuid_get_error() (#188) * Support for Intel Alder Lake-N * Support for AMD Rembrandt with Radeon Graphics * Support for Intel Raptor Lake-S with "Golden Cove" cores * Support for Intel Raptor Lake-P * Support for Intel Raptor Lake-U * Support for Intel Rocket Lake-E ------------------------------------------------------------------- Fri Dec 2 21:09:08 UTC 2022 - Dirk Müller <dmueller@suse.com> - update to 0.6.2: * Support for AMD Raphael * Support for AMD Dali * Support for AMD Van Gogh * Fix stuck cpuid_tool due to set_cpu_affinity() on Windows (#172) * Remove AMD Warhol from DB (Zen3+ cancelled) * Fix physical core count computed by cpu_identify_all() when HT is disabled (#175) * Fix shared library symlinks with CMake (#174) * Support for Intel Raptor Lake-S * Fix segmentation fault in cpu_identify_all() for single-core CPUs * Support for Intel Penryn L * Support for Intel Tremont * Support for AMD Mendocino * Support for Intel Ice Lake (Xeon-D) * Support for AMD Zen 2 Desktop Kit CPUs (4700S + 4800S) * Support for AMD Athlon 64 Sherman ------------------------------------------------------------------- Wed Oct 12 10:25:10 UTC 2022 - Martin Pluskal <mpluskal@suse.com> - Add missing dependency ------------------------------------------------------------------- Sat Oct 1 07:59:30 UTC 2022 - Dirk Müller <dmueller@suse.com> - update to 0.6.0: * Support for AMD Rembrandt * Support for AMD Warhol * Remove Debian package from source tree (#165) * Fix build under Clang 15 (#167) * Support for AMD Athlon Godavari * Support for hybrid CPU like Intel Alder Lake (#166) * Detect presence of hypervisor (#169) * Decode deterministic cache info for AMD CPUs (#168) * Add cache instances field in cpu_id_t and system_id_t (#168) * Support AMD Bald Eagle * Support for more AMD Godavari (Athlon) * Rename AMD Bulldozer to Zambezi * Support for AMD Interlagos * Support for AMD Abu Dhabi * Support for AMD Beema * Support for AMD Steppe Eagle * Support for more AMD Kabini (Sempron + Athlon) * Improve msr_serialize_raw_data() * Support for AMD Zen 2 custom APU for Steam Deck ------------------------------------------------------------------- Wed Feb 9 12:40:00 UTC 2022 - Martin Pluskal <mpluskal@suse.com> - Update to version 0.5.1+git.1644144775: * Tests: add more Zen2 tests from InstLatx64 * DB: add Lucienne * Report memory allocation failures without segfaulting. (#160) * Don't link with msrdriver.c on non-Windows platform. (#159) ------------------------------------------------------------------- Fri Aug 27 08:35:35 UTC 2021 - Martin Pluskal <mpluskal@suse.com> - Update to version 0.5.1+git.1626502835: * CMake: reduce min cmake requirement 3.14 -> 3.13 * Fix failing CI builds introduced by cb5fdd1 * Use popcount64 from libc when available (#152) * allow to build either static or shared (#156) * cmake: allow libcpuid to be added as a CMake subproject (#155) * fix installation of BUNDLE if iOS (#154) * cmake: add an option to build tests (#153) * Fix #150: CPU Family/Model is used as Ext.Family/Model * DB: add Tiger Lake ------------------------------------------------------------------- Fri Mar 26 09:34:52 UTC 2021 - Martin Pluskal <mpluskal@suse.com> - Update to version 0.5.1+git.1616323866: * Doxygen: remove deprecated option * Release version 0.5.1 (#151) * Tests: fix truncation warnings in convert_instlatx64 * Fix warning with a comment * DB: add Rocket Lake * DB: add Milan * Tests: fix --create argument in convert_instlatx64 tool * DB: add Cezanne * DB: add Xeon E3 1275 * CI: use microsoft/setup-msbuild@v1.0.2 * CI: fix deprecated commands * Tests: add Core i5 8265U (Whiskey Lake-U) * DB: add Whiskey Lake-U ------------------------------------------------------------------- Tue Nov 24 09:45:35 UTC 2020 - Martin Pluskal <mpluskal@suse.com> - Update to version 0.5.0+git.20201114: * Tests: fix path for cpuid_tool When we use CMake, the 'cpuid_tool' binary is in the 'build' directory * DB: add Vermeer https://en.wikichip.org/wiki/amd/cores/vermeer Test file converted from http://users.atw.hu/instlatx64/AuthenticAMD/AuthenticAMD0A20F10_K19_Vermeer_CPUID1.txt * DB: add Gemini Lake https://en.wikichip.org/wiki/intel/cores/gemini_lake Reported in X0rg/CPU-X#164 * DB: add Comet Lake-U https://en.wikipedia.org/wiki/Comet_Lake_(microprocessor)#U-series_(Medium_power) Reported in X0rg/CPU-X#162 * DB: add Kaby Lake-G https://en.wikichip.org/wiki/intel/cores/kaby_lake_g Test file converted from http://users.atw.hu/instlatx64/GenuineIntel/GenuineIntel00906E9_KabylakeG_CPUID.txt * DB: add Kaby Lake Refresh https://en.wikichip.org/wiki/intel/cores/kaby_lake_r Core i5 8250U was detected as Coffee Lake wrongly. Reported in X0rg/CPU-X#161 ------------------------------------------------------------------- Thu Nov 5 08:47:16 UTC 2020 - Martin Pluskal <mpluskal@suse.com> - Update to version 0.5.0+git.20201019: * Fixes issue #148: CMake build script not in 0.5.0 tarball release ------------------------------------------------------------------- Thu Aug 13 11:17:44 UTC 2020 - Martin Pluskal <mpluskal@suse.com> - Update to version 0.5.0+git.20200528: * Related to c2645d0. Convert all python scripts to Python 3. * Add Downloads section on Readme.md Close #140 * Add I-Nex to the users list ------------------------------------------------------------------- Tue May 26 12:21:20 UTC 2020 - Martin Pluskal <mpluskal@suse.com> - Update to version v0.5.0+git.20200526: * CI: remove 'v' prefix in assets * CI: checkout sources before making release * Release version 0.5.0 (#146) * Add GitHub workflows for CI/CD - CI: it will check code consistency and run tests for all events (except for tags) - CD: it will build all assets and create a draft Close #122 * check-consistency: return error count * Fix code consistency Result before this patch: * CMake: fix include directory * CMake: fix build on Windows * CMake: fix install target's export * tests: fix unused-result warning in convert_instlatx64 tool * Update .gitignore * CMake: fix Unix install and format * Add config file for cmake-format It formats CMakeLists.txt files See https://github.com/cheshirekow/cmake_format * Doxygen: upgrade Doxyfile to avoid warnings warning: Tag 'PERL_PATH' at line 1032 of file '/libcpuid/build/libcpuid/Doxyfile' has become obsolete. To avoid this warning please remove this line from your configuration file or upgrade it using "doxygen -u" warning: argument 'a4wide' for option PAPER_TYPE is not a valid enum value Using the default: a4! * Doxygen: turn on quiet mode It is too noisy with CMake * Detect AVX512VBMI and AVX512VBMI2 features on Intel CPUs More information: https://en.wikichip.org/wiki/x86/avx-512 Resolve #134 * Detect ABM feature on Intel CPUs Resolve #144 * Detect RDSEED/ADX/SHA_NI features on AMD CPUs These x86 instruction set extensions are present since Zen micro-architecture Resolve #145 * Update cpuid_main.c * DB: add Ivy Bridge-E (Xeon) * Tests: update all tests to add fields for L1I * Tests: update to add L1I information Related to 25d0614811991c855ce7db0d898dbc6200dfa840 Dump of Core i5 520m from CPU-X#119 * Add L1 Instruction Cache information Some CPUs does not have the same associativity for L1D and L1I, as reported in X0rg/CPU-X#119 It adds l1_instruction_assoc and l1_instruction_cacheline in cpu_id_t To avoid confusing, also adds l1_data_assoc and l1_data_cacheline l1_assoc and l1_cacheline are leave untouched for backward compatibility * Ignore .vscode directory Yes, 0b05f45e03b0aa39a65eba9451b59c9381e8474c was about VS Code * Tests: add amd_fn8000001dh subleaf See e562798cecf4af852fdfef4b0e7bf159a5d9b4de * Tests: parse subleafs in convert_instlatx64 Also, it adds 0xffffffff when data is not available, so all lines are presents * Re-fix L3 cache associativity detection on AMD Zen 2 CPUs Previous commit: 848394ee460c70298f91569d33f2c156bddb0f6c * Applied a patch from @tavplubix * Use constant for registers name It helps when reading technical documentation and it avoids 'magic values' * Remove all trailling spaces It is annoying with some text editors * DB: fix Rome extended model * DB: add Renoir APUs * Tests: add Core i5 8250U Related to X0rg/CPU-X#129 * DB: add Ice Lake CPUs * DB: add Comet Lake CPUs * DB: add Coffee Lake Refresh It differs from Coffee Lake by stepping Core i5 9400 and 9500 will still be detected as Coffee Lake because it only differs by revision... * DB: add Coffee Lake-U It differs from Kaby Lake-U by stepping * DB: add Cannon Lake CPUs * DB: clarify Intel Generations * tests: remove duplicate addresses in RAW part * tests: fix convert_instlatx64 tool * Fix L3 cache associativity detection on AMD Zen 2 CPUs * Fix CMake * Add CMake * Add CMake ------------------------------------------------------------------- Thu Jan 23 10:08:59 UTC 2020 - Martin Pluskal <mpluskal@suse.com> - Update to version 0.4.1+git.20200102: * DB: Add Threadripper (Castle Peak) * Fix compilation on non-x86/ARM architectures. * Add support for get_total_cpus on Haiku. * Some typo fixes in human readable text. * Add Xeon CLX (Cascade lake-based) using data from PR #129 * add support to feature intel avx512_vnni * AARCH64 stub * Ignore convert_instlatx64 binary * add Hygon Dhyana C86 7seris test file * Add Hygon Dhyana detect support - Switch to _service ------------------------------------------------------------------- Fri Feb 15 13:00:06 UTC 2019 - Jan Engelhardt <jengelh@inai.de> - Use noun phrase in summaries. ------------------------------------------------------------------- Thu Feb 14 14:12:46 UTC 2019 - Martin Pluskal <mpluskal@suse.com> - Update to version 0.4.1: * Better support for Skylake Core i5 (#76) * Misdiagnosis microarchitecture for i3-3220T (#81) * Ability to dump MSR values to a file (PR #82) * AMD Ryzen support (#86) * Support for Coffee and Kaby Lake (#104) * Support for Raven Ridge and Threadripper (#106) * Support for Pinnacle Ridge (#111) * Fix P-III Celeron misdetection * Support for Skylake-X (#116) * Support for Zen+ Threadripper ------------------------------------------------------------------- Thu Jun 8 13:22:59 UTC 2017 - mpluskal@suse.com - Enable internal tests ------------------------------------------------------------------- Mon Nov 28 09:18:18 UTC 2016 - mpluskal@suse.com - Update to version 0.4.0: * A backwards-incompatible change, since the sizeof cpu_raw_data_t and cpu_id_t are now different. * Better detection of AMD clock multiplier with msrinfo. * Support for Intel SGX detection - Some packaging cleanups * Use url as source * Split binary from devel package ------------------------------------------------------------------- Sun Oct 16 13:40:44 UTC 2016 - dap.darkness@gmail.com - Update from 0.1.0 to 0.3.0: * Added intel_fn11 fields to cpu_raw_data_t to handle new processor topology enumeration required on Core i7 * Support for Intel Nehalem architecture CPUs (Core i7, Xeon i7) * Added support for greater more accurate CPU clock measurements with cpu_clock_by_ic() * Support for AMD Bulldozer CPUs, 128-bit SSE unit size checking. A backwards-incompatible change, since the sizeof cpu_id_t is now different. * Support for Ivy Bridge, and detecting the presence of the RdRand instruction. * Support for newer processors up to Haswell and Vishera * Fix clock detection in cpu_clock_by_ic() for Bulldozer * Support for detection of AVX/AVX2/BMI1/BMI2 * More entries supported in cpu_msrinfo() * Rename of some CPU codenames, made more consistent * *BSD and Solaris support (unofficial) * A backwards-incompatible change, since the sizeof cpu_raw_data_t and cpu_id_t are now different. * Support for processors up to Skylake. * Fix clock detection in cpu_clock_by_ic() for Skylake. * Support up to 8 subleaf entries for CPUID leaf 04 and detection of L4 cache. * MSR functions supported on FreeBSD. * INFO_VOLTAGE request supported by cpu_msrinfo(). ------------------------------------------------------------------- Mon Aug 18 15:06:16 UTC 2014 - dap.darkness@gmail.com - Updated to resolve "W: file-contains-current-date". ------------------------------------------------------------------- Thu Jul 31 15:07:19 UTC 2014 - dap.darkness@gmail.com - Updated from https://github.com/anrieff/libcpuid ------------------------------------------------------------------- Sun Feb 2 13:39:36 UTC 2014 - dap.darkness@gmail.com - Initial build.
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