File CoreFreq.changes of Package CoreFreq

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File CoreFreq.changes of Package CoreFreq (Revision ffee7aff5f3d3fa2acb59027a11fed40)

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Fri Jan  6 10:44:12 UTC 2023 - Dirk Müller <dmueller@suse.com>

- update to 1.94.3:
  * [AMD][RMB] If UMC is quad channels then unpopulate odd channels
  * [AMD][RPL] Provide Service Processor Vcore as workaround
  * [UI] Auto size and lay performance capabilities window
  * [UI] Adding comments to the EEO and R2H technologies
  * [AMD][Raphael] 7950X3D, 7900X3D. support

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Tue Jan  3 08:19:37 UTC 2023 - Dirk Müller <dmueller@suse.com>

- update to 1.94.1:
  * [Intel] Gemini Lake
  * [AMD] Ryzen 5 6600 H SoC, UMC channels
  * [AMD] Rembrandt: maximum of two UMC channels
  * [AMD] Raphael: Decodes DIMM geometry from AddrCfg
  * [AMD] Zen: Aggregation refactored
  * [AMD] Improved DDR5 clock decoding
  * Optimized Idle Loop

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Tue Dec 13 22:58:21 UTC 2022 - Michael Pujos <pujos.michael@gmail.com>

- removed modprobe_corefreqd.service.patch and harden_corefreqd.service.patch
  now included in new corefreqd.service file replacing stock one  
- update to 1.93.1
  * [PRJ] CoreFreq version 1.93.1
  * [ACPI/CPPC/EPP] Preview of AMD/Zen Energy Preference (CONFIG_CACHY)
  * [UI] Changed the HWP or CPPC ratio bounds.
  * [FIX] Putting `corefreqd` in the root cgroup (issue #379) Thanks to gel-crabs
  * [DOC] Parameters to blacklist the amd_pstate since kernel 6.0.11
  * [AMD][Zen4] Apply a voltage formula based on Rembrandt's. (#378)
  * [AMD][Zen4/Raphael] Attempting temperature per CCD from TCTL+0x308
  * [AMD][Zen4] Changed Timer loop
  * [CR] CLI code review and UI optimizations
  * [UI] Auto refresh the Topology items when off/online
  * [CR] Conditionally build with additional PMC Counters
  * [Intel] Adding Z8000 System Memory Controller Registers
  * [CR] Transformed global variable in cells padding
  * [UI] Windows re-scaling fix
  * [UI] Apply color theming to the CPPC capabilities list.
  * [AMD][Raphael] Adding device DIDs to probe UMC and IOMMU
  * [CPPC/FMW] Computes value bounds while Enabling/Disabling firmware
  * [CR] CPPC lib errors are now raised to Debug level
  * [AMD][Zen4] Increased the UMC size to 12 channels.
  * [CPPC] Handles the OffLine CPU case.
  * [CLI] Refactoring HWP/CPPC to print all capabilities per CPU
  * [ACPI] Computes the CPPC Bounds
  * [Intel] Linear Address Masking (LAM)
  * [CLI] EFER: Left aligned labels
  * [AMD] Reports UAIE and AIBRSE bits from EFER system register
  * [CLI] Changed mitigation mechanisms incapability labels
  * [AMD][Zen2] Mitigation Mechanism BTC-NOBR * ACPI/OSPM documentation
  * [CR] Code review on bit masks
  * [CPPC][ACPI] Kernel may decode the Guaranteed Performance Register
  * [UI] Optimize the cycles to clear the time bar.
  * [CR] Code review for extra compiler warnings
  * [UI] Time of the day displayed in the right side of menu
  * [UI] Display the current date and time in menu bar
  * [Kernel] Introducing support of `CONFIG_SCHED_BORE`
  * [CLI] Fixing ambiguous CPPC report: hardware vs firmware
  * [CLI] Surrounds _CPC feature with square brackets
  * [CPPC] Provides the ACPI _CPC object state.
  * [UI] Colors the task being tracked in the tracking list
  * [UI] Display the current time in the menu bar
  * [CLI] Reserve the programmable TDP section to Intel processors.
  * [AMD/Zen3+] Improving the DIMM geometry of Rembrandt UMC

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Mon Dec  5 08:53:55 UTC 2022 - Dirk Müller <dmueller@suse.com>

- update to 1.92.4:
  * [Intel/Skylake-X] Permits MSR_RING_PERF_LIMIT_REASONS

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Fri Nov  4 14:32:03 UTC 2022 - Jan Engelhardt <jengelh@inai.de>

- Repair deficient description grammar.

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Fri Nov  4 13:35:40 UTC 2022 - Michael Pujos <pujos.michael@gmail.com>

- update to version 1.92.3
  - Export CPUID bits Intel Sierra Forest, Grand Ridge, Granite Rapids
    and completes AMD64 Fn0000_0007_ECX_x0
  - [Features] WBNOINVD and CLZERO instructions
  - Adding various Mitigation Mechanism aggregations:
    IPRED_DIS_U, IPRED_DIS_S, RRSBA_DIS_U, RRSBA_DIS_S, BHI_DIS_S, MCDT_NO
  - RDPID and UMIP capability fixed.
  - [AMD] Perf. Mon. version based on CPUID_0x80000022.EAX.PerfMonV2
  - [AMD][Zen3+][Rembrandt] Trigger UMC and IOMMU decoders
  - [AMD][Ryzen 5 6600H] Found voltage VID @ SMU 0x6f010 and 0x6f014
  - Introducing AMD Security Feature capabilities:
    SKINIT, SEV, GMET, SEV-ES, SEV-SNP
  - [AMD64] Non-architectural MSR: SPECULATIVE STORE BYPASS DISABLE
  - [Intel][2nd & 3rd gen] Misc IMC optimizations
  - [AMD][Rembrandt] Provides Vcore from a new formula.
  - Dumping CPUID leaves from AMD64 Architecture Programmer’s Manual
  - [Intel][HSW & BDW] Compute the DIMM banks
  - [UI] Re-assigned keys to move or resize windows.
  - [AMD][Zen] Uncore frequency: Improving the Memory Clock divisor
  - [Intel][HSW & BDW][SKL] Make use of same function DimmWidthToRows 
  - [AMD][Zen3+][Rembrandt] Provides the thermal sensor.
  - [AMD/Zen2 & Zen3] Removed the HSMP capability.
  - [Intel][CML][RKL][TGL] Compute the DIMM Rows from CH_WIDTH
  - [AMD/EPYC] Adding the CPUID of Zen4 Genoa architecture
  - [AMD/Zen2] Introducing Mendocino architecture
  - Changed MeteorLake/N to CPUID 06_B5
  - [Intel] Computes BIOS DRAM frequency based on PLL_REF100
  - [Intel][SNB/IVB/HSW/BDW] Improved BIOS DRAM frequency
  - [Intel][SNB/IVB] DRAM frequency based on RAM_Select and FSB_Select
  - [Intel][IVB] IMC specifications and optimizations.
  - [Intel][SNB,IVB] Computes the DIMM A from DAS bit in MAD register
  - [Intel][SNB,IVB,HSW,BDW] Rolling back changes to the DIMM topology
  - [Intel][BDW][HSW] Query the IMC Power Down Mode
  - [Intel][IVB][SNB] Attempt to decode the IMC third timings 
  - [AMD][Ryzen] Added AMD Ryzen 7 PRO 6860Z
  - [AMD][F17h-F19h] Can toggle ON and OFF the Instruction Cache Unit 
  - [AMD] Checking the Ryzen "OEM Only" processors
  - [Intel] Specification of 12th Gen. MSR registers capability
  - [Intel] Adding Raptor Lake-S with CPUID 06_BF
  - [AMD] Introducing Zen 4 / Raphael architecture
  - [Intel][SNB,IVB,HSW] Attempt to assign the Rank per DIMM slot
  - [Intel][SNB,IVB,HSW] Attempt to fix the DIMM(s) topology layout
  - ClockSource: TSC udelay() asm implementation builtin as a default
  - [Intel][Alder Lake] Adding IMC entry for i5-12500 processor
  - [Intel][Alder Lake] Added default case if Processor has only Pcores
  - [Intel][Atom/Bonnell][IMC] Attempt to compute the DIMM geometry
  - [UI][Custom view] Show the Uncore unit in watt or joule
  - [UI] Display HWP or CPPC in footer for capable processors.
  - [CLI] Added HWP Capabilities and HWP Request to the JSON export
  - [CLI] Don't allow the HWP dialog box if feature is not available.
  - [CPPC][Firmware] allows (de)activation of the feature.
  - [CLI] Added CPU ratios to JSON export
  - [CPPC] Improved scaling
  - [CPPC] Build fixed down to Kernel version 3
  - [Kernel/ACPI] Attempt to write CPPC registers

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Mon Aug 22 15:48:08 UTC 2022 - Michael Pujos <pujos.michael@gmail.com>

- Update to version 1.91.6
  - [AMD/Zen][UMC] Fixed the Mem Clock and ECC regressions
  - Designate the Package identifier in Power consumed readings
  - [Intel/ADL/IMC] Guessing activated channel from the populated DIMM
  - [AMD][UMC, IOMMU] Adding missing DID of family 19h devices
  - [AMD_DataFabric_Cezanne] Removed the Experimental mode
  - Intel/ADL/IMC: Fixing the Memory Channels count
  - [AMD/Zen] Improved UMC mapping. Threadripper 3960X issue
  - Avoid some NULL pointer strings during SMBIOS decoding
  
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Wed Jun 22 19:35:21 UTC 2022 - Michael Pujos <pujos.michael@gmail.com>

- Update to version 1.91.3
  * No changelog was made available by upstream

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Mon Mar  7 11:57:34 UTC 2022 - Michael Pujos <pujos.michael@gmail.com>

- removed non-working leap15_2.patch and leap15_3.patch:
  Leap 15.4 is the minimum supported version
- Update to version 1.90.1
  * support for Alder Lake architecture:
    in particular, specialized monitoring for Pcore and Ecore
  * more precise DDR5 and DDR4 timings from SKL to ADL:
    introduction of "Gear mode"
  * improvement using Power Limiters:
    zero W on PL1 & PL2; DRAM clampig marked experimental
  * characteristics for Zen architecture:
    CPPC; C1E; MEM CLOCK in raw frequency
  * C-state Core for Ice Lake/X
  * various characteristics of C-state package for AMD/Zen and Intel (Lake)
  * various changes in UI
  * non-regression tests for kernels 5.16.12 and 5.17.rc6

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Sat Feb 12 22:26:56 UTC 2022 - Michael Pujos <pujos.michael@gmail.com>

- Update to version 1.89.3
  * No changelog was made available by upstream
  
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Sun Oct 10 14:37:04 UTC 2021 - Michael Pujos <pujos.michael@gmail.com>

- Update to version 1.87.4
- fixed service hardening preventing daemon to start (boo#1191509) 
- added modprobe_corefreqd.service.patch to load/unload kernel
  module on service start/stop. Do not load module on boot anymore
- fixed leap15_3.patch including unnessary junk

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Tue Sep  7 10:17:46 UTC 2021 - Michael Pujos <pujos.michael@gmail.com>

- Update to version 1.87.1

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Tue Jul 27 09:50:10 UTC 2021 - Johannes Segitz <jsegitz@suse.com>

- Added hardening to systemd service(s). Added harden_corefreqd.service.patch

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Sat Jul  3 13:22:03 UTC 2021 - Ferdinand Thiessen <rpm@fthiessen.de>

- Update to version 1.86.7
  * AMD/Zen: Improve SMT counters built on VPMC
  * AMD/Matisse & Zen3: Can alter the Power Limit with a PL1 offset
  * AMD/SMU: Provides the firmware and interface version
  * AMD HSMP: Support Host System Management Port.
  * AMD IOMMU Base Address Register fix.
  * Intel/Nehalem: Altering the TDC limit
  * Intel: Integration of the 11th Generation
  * UI: Stream buffer memory overlap fix.
  * UI: Support color theming and introducing the Strawberry theme.
  * Driver: New 'CPU_Count' argument
  * New parameter "WDT_Enable" to toggle the Watchdog Timer.
  * Page fault fix when unregistering idle device percpu structure
  * Avoid a kernel zero division in clocksource_register_khz()
  * Various bug fixes and minor improvements

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Sat May  8 12:00:09 UTC 2021 - Michael Pujos <pujos.michael@gmail.com>

- updated to v1.84.5
  Fixes compilation on kernel 5.12
  See commits on https://github.com/cyring/CoreFreq/commits/master
  for full change list
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Thu Apr 15 09:55:08 UTC 2021 - Michael Pujos <pujos.michael@gmail.com>

- updated to v1.84.1
  See commits on https://github.com/cyring/CoreFreq/commits/master
  for changes list
- added patch leap15_3.patch: fix failure to build on Leap 15.3

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Thu Dec 31 14:56:39 UTC 2020 - Michael Pujos <pujos.michael@gmail.com>

- updated to git 20201229.
  See commits on https://github.com/cyring/CoreFreq/commits/master
  for changes list

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Wed Oct 28 12:43:05 UTC 2020 - Michael Pujos <pujos.michael@gmail.com>

- updated to git 20201028, fixes compilation on kernel 5.9

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Mon Sep 14 19:33:07 UTC 2020 - Michael Pujos <pujos.michael@gmail.com>

- updated changelog to mention leap15_2.patch

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Mon Sep 14 11:25:44 UTC 2020 - Michael Pujos <pujos.michael@gmail.com>

- updated to git 20200914, fixes compilation on kernel 5.8

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Tue Aug 18 15:31:19 UTC 2020 - Dominique Leuenberger <dimstar@opensuse.org>

- Fix invalid usage of %{_libexecdir} for systemd owned paths below
  %{_prefix}/lib.

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Tue Jul 14 13:41:15 UTC 2020 - Michael Pujos <pujos.michael@gmail.com>

- added patch leap15_2.patch: fix failure to build on Leap 15.2
- fix failure to build on Tumbleweed
- updated to 1.79.9 + current git

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Fri Apr 17 22:50:23 UTC 2020 - Michael Pujos <pujos.michael@gmail.com>

- updated to 1.75.2 current git to fix compilation on kernel 5.6.x

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Thu Mar  5 10:38:04 UTC 2020 - Michael Pujos <pujos.michael@gmail.com>

- updated to 1.73.7
- do not use git version anymore
- added %systemd_requires
- remove unneeded unzip BuildRequires

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Wed Feb 19 22:53:29 UTC 2020 - Michael Pujos <pujos.michael@gmail.com>

- Initial version from git 20200219

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