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xen.7985
5b02c786-x86-Intel-mitigations-for-GPZ-SP4.patch
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File 5b02c786-x86-Intel-mitigations-for-GPZ-SP4.patch of Package xen.7985
# Commit 9df52a25e0e95a0b9971aa2fc26c5c6a5cbdf4ef # Date 2018-05-21 14:20:06 +0100 # Author Andrew Cooper <andrew.cooper3@citrix.com> # Committer Andrew Cooper <andrew.cooper3@citrix.com> x86/Intel: Mitigations for GPZ SP4 - Speculative Store Bypass To combat GPZ SP4 "Speculative Store Bypass", Intel have extended their speculative sidechannel mitigations specification as follows: * A feature bit to indicate that Speculative Store Bypass Disable is supported. * A new bit in MSR_SPEC_CTRL which, when set, disables memory disambiguation in the pipeline. * A new bit in MSR_ARCH_CAPABILITIES, which will be set in future hardware, indicating that the hardware is not susceptible to Speculative Store Bypass sidechannels. For contemporary processors, this interface will be implemented via a microcode update. Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com> Reviewed-by: Jan Beulich <jbeulich@suse.com> --- a/docs/misc/xen-command-line.markdown +++ b/docs/misc/xen-command-line.markdown @@ -496,9 +496,10 @@ accounting for hardware capabilities as Currently accepted: -The Speculation Control hardware features `ibrsb`, `stibp`, `ibpb` are used by -default if avaiable. They can be ignored, e.g. `no-ibrsb`, at which point Xen -won't use them itself, and won't offer them to guests. +The Speculation Control hardware features `ibrsb`, `stibp`, `ibpb`, `ssbd` are +used by default if available and applicable. They can be ignored, +e.g. `no-ibrsb`, at which point Xen won't use them itself, and won't offer +them to guests. ### cpuid\_mask\_cpu (AMD only) > `= fam_0f_rev_c | fam_0f_rev_d | fam_0f_rev_e | fam_0f_rev_f | fam_0f_rev_g | fam_10_rev_b | fam_10_rev_c | fam_11_rev_b` @@ -1751,7 +1752,7 @@ protect itself, and Xen's ability to vir respectively. * `msr-sc=` offers control over Xen's support for manipulating MSR\_SPEC\_CTRL on entry and exit. These blocks are necessary to virtualise support for - guests and if disabled, guests will be unable to use IBRS/STIBP/etc. + guests and if disabled, guests will be unable to use IBRS/STIBP/SSBD/etc. * `rsb=` offers control over whether to overwrite the Return Stack Buffer / Return Address Stack on entry to Xen. @@ -1773,7 +1774,8 @@ prediction barriers on vcpu context swit On hardware supporting SSBD (Speculative Store Bypass Disable), the `ssbd=` option can be used to force or prevent Xen using the feature itself. On AMD hardware, this is a global option applied at boot, and not virtualised for -guest use. +guest use. On Intel hardware, the feature is virtualised for guests, +independently of Xen's choice of setting. ### sync\_console > `= <boolean>` --- a/tools/libxl/libxl_cpuid.c +++ b/tools/libxl/libxl_cpuid.c @@ -205,6 +205,7 @@ int libxl_cpuid_parse_config(libxl_cpuid {"ibrsb", 0x00000007, 0, CPUID_REG_EDX, 26, 1}, {"stibp", 0x00000007, 0, CPUID_REG_EDX, 27, 1}, {"arch-caps", 0x00000007, 0, CPUID_REG_EDX, 29, 1}, + {"ssbd", 0x00000007, 0, CPUID_REG_EDX, 31, 1}, {"lahfsahf", 0x80000001, NA, CPUID_REG_ECX, 0, 1}, {"cmplegacy", 0x80000001, NA, CPUID_REG_ECX, 1, 1}, --- a/tools/misc/xen-cpuid.c +++ b/tools/misc/xen-cpuid.c @@ -166,8 +166,7 @@ static const char *str_7d0[32] = [26] = "ibrsb", [27] = "stibp", [28] = "REZ", [29] = "arch_caps", - - [30 ... 31] = "REZ", + [30] = "REZ", [31] = "ssbd", }; static struct { --- a/xen/arch/x86/cpuid.c +++ b/xen/arch/x86/cpuid.c @@ -43,6 +43,11 @@ static int __init parse_xen_cpuid(const if ( !val ) setup_clear_cpu_cap(X86_FEATURE_STIBP); } + else if ( (val = parse_boolean("ssbd", s, ss)) >= 0 ) + { + if ( !val ) + setup_clear_cpu_cap(X86_FEATURE_SSBD); + } else rc = -EINVAL; --- a/xen/arch/x86/spec_ctrl.c +++ b/xen/arch/x86/spec_ctrl.c @@ -192,26 +192,31 @@ static void __init print_details(enum in printk("Speculative mitigation facilities:\n"); /* Hardware features which pertain to speculative mitigations. */ - printk(" Hardware features:%s%s%s%s%s%s\n", + printk(" Hardware features:%s%s%s%s%s%s%s%s\n", (_7d0 & cpufeat_mask(X86_FEATURE_IBRSB)) ? " IBRS/IBPB" : "", (_7d0 & cpufeat_mask(X86_FEATURE_STIBP)) ? " STIBP" : "", + (_7d0 & cpufeat_mask(X86_FEATURE_SSBD)) ? " SSBD" : "", (e8b & cpufeat_mask(X86_FEATURE_IBPB)) ? " IBPB" : "", (caps & ARCH_CAPABILITIES_IBRS_ALL) ? " IBRS_ALL" : "", (caps & ARCH_CAPABILITIES_RDCL_NO) ? " RDCL_NO" : "", - (caps & ARCH_CAPS_RSBA) ? " RSBA" : ""); + (caps & ARCH_CAPS_RSBA) ? " RSBA" : "", + (caps & ARCH_CAPS_SSB_NO) ? " SSB_NO" : ""); /* Compiled-in support which pertains to BTI mitigations. */ if ( IS_ENABLED(CONFIG_INDIRECT_THUNK) ) printk(" Compiled-in support: INDIRECT_THUNK\n"); /* Settings for Xen's protection, irrespective of guests. */ - printk(" Xen settings: BTI-Thunk %s, SPEC_CTRL: %s, Other:%s\n", + printk(" Xen settings: BTI-Thunk %s, SPEC_CTRL: %s%s, Other:%s\n", thunk == THUNK_NONE ? "N/A" : thunk == THUNK_RETPOLINE ? "RETPOLINE" : thunk == THUNK_LFENCE ? "LFENCE" : thunk == THUNK_JMP ? "JMP" : "?", !use_spec_ctrl ? "No" : (default_xen_spec_ctrl & SPEC_CTRL_IBRS) ? "IBRS+" : "IBRS-", + !use_spec_ctrl || !boot_cpu_has(X86_FEATURE_SSBD) + ? "" : + (default_xen_spec_ctrl & SPEC_CTRL_SSBD) ? " SSBD+" : " SSBD-", opt_ibpb ? " IBPB" : ""); /* @@ -480,6 +485,10 @@ void __init init_speculation_mitigations } } + /* If we have SSBD available, see whether we should use it. */ + if ( boot_cpu_has(X86_FEATURE_SSBD) && use_spec_ctrl && opt_ssbd ) + default_xen_spec_ctrl |= SPEC_CTRL_SSBD; + /* * PV guests can poison the RSB to any virtual address from which * they can execute a call instruction. This is necessarily outside --- a/xen/include/asm-x86/msr-index.h +++ b/xen/include/asm-x86/msr-index.h @@ -35,6 +35,7 @@ #define MSR_SPEC_CTRL 0x00000048 #define SPEC_CTRL_IBRS (_AC(1, ULL) << 0) #define SPEC_CTRL_STIBP (_AC(1, ULL) << 1) +#define SPEC_CTRL_SSBD (_AC(1, ULL) << 2) #define MSR_PRED_CMD 0x00000049 #define PRED_CMD_IBPB (_AC(1, ULL) << 0) @@ -43,6 +44,7 @@ #define ARCH_CAPABILITIES_RDCL_NO (_AC(1, ULL) << 0) #define ARCH_CAPABILITIES_IBRS_ALL (_AC(1, ULL) << 1) #define ARCH_CAPS_RSBA (_AC(1, ULL) << 2) +#define ARCH_CAPS_SSB_NO (_AC(1, ULL) << 4) /* Intel MSRs. Some also available on other CPUs */ #define MSR_IA32_PERFCTR0 0x000000c1 --- a/xen/include/public/arch-x86/cpufeatureset.h +++ b/xen/include/public/arch-x86/cpufeatureset.h @@ -245,6 +245,7 @@ XEN_CPUFEATURE(AVX512_4FMAPS, 9*32+ 3) / XEN_CPUFEATURE(IBRSB, 9*32+26) /*A IBRS and IBPB support (used by Intel) */ XEN_CPUFEATURE(STIBP, 9*32+27) /*A! STIBP */ XEN_CPUFEATURE(ARCH_CAPS, 9*32+29) /* IA32_ARCH_CAPABILITIES MSR */ +XEN_CPUFEATURE(SSBD, 9*32+31) /* MSR_SPEC_CTRL.SSBD available */ #endif /* XEN_CPUFEATURE */ --- a/xen/tools/gen-cpuid.py +++ b/xen/tools/gen-cpuid.py @@ -257,10 +257,19 @@ def crunch_numbers(state): AVX512BW, AVX512VL, AVX512VBMI, AVX512_4VNNIW, AVX512_4FMAPS, AVX512_VPOPCNTDQ], - # Single Thread Indirect Branch Predictors enumerates a new bit in the - # MSR enumerated by Indirect Branch Restricted Speculation/Indirect - # Branch Prediction Barrier enumeration. - IBRSB: [STIBP], + # The features: + # * Single Thread Indirect Branch Predictors + # * Speculative Store Bypass Disable + # + # enumerate new bits in MSR_SPEC_CTRL, which is enumerated by Indirect + # Branch Restricted Speculation/Indirect Branch Prediction Barrier. + # + # In practice, these features also enumerate the presense of + # MSR_SPEC_CTRL. However, no real hardware will exist with SSBD but + # not IBRSB, and we pass this MSR directly to guests. Treating them + # as dependent features simplifies Xen's logic, and prevents the guest + # from seeing implausible configurations. + IBRSB: [STIBP, SSBD], } deep_features = tuple(sorted(deps.keys()))
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