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SUSE:SLE-12-SP1:GA
qemu-linux-user.6354
0440-i386-kvm-MSR_IA32_SPEC_CTRL-and-MSR.patch
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File 0440-i386-kvm-MSR_IA32_SPEC_CTRL-and-MSR.patch of Package qemu-linux-user.6354
From f8aca9c25d9669536fdcbbf17527526635580e72 Mon Sep 17 00:00:00 2001 From: Wei Wang <wei.w.wang@intel.com> Date: Tue, 7 Nov 2017 16:39:49 +0800 Subject: [PATCH] i386/kvm: MSR_IA32_SPEC_CTRL and MSR_IA32_PRED_CMD CPUID(EAX=0X7,ECX=0).EDX[26]/[27] indicates the support of MSR_IA32_SPEC_CTRL and MSR_IA32_PRED_CMD. Expose the CPUID to the guest. Also add the support of transferring the MSRs during live migration. Signed-off-by: Wei Wang <wei.w.wang@intel.com> [BR: BSC#1068032 CVE-2017-5715] Signed-off-by: Bruce Rogers <brogers@suse.com> --- target-i386/cpu.c | 3 ++- target-i386/cpu.h | 5 +++++ target-i386/kvm.c | 14 ++++++++++++++ target-i386/machine.c | 21 +++++++++++++++++++++ 4 files changed, 42 insertions(+), 1 deletion(-) diff --git a/target-i386/cpu.c b/target-i386/cpu.c index 486828064d..29783d7a7e 100644 --- a/target-i386/cpu.c +++ b/target-i386/cpu.c @@ -2199,10 +2199,11 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, case 7: /* Structured Extended Feature Flags Enumeration Leaf */ if (count == 0) { + host_cpuid(index, 0, eax, ebx, ecx, edx); *eax = 0; /* Maximum ECX value for sub-leaves */ *ebx = env->features[FEAT_7_0_EBX]; /* Feature flags */ *ecx = 0; /* Reserved */ - *edx = 0; /* Reserved */ + *edx &= CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_PRED_CMD; } else { *eax = 0; *ebx = 0; diff --git a/target-i386/cpu.h b/target-i386/cpu.h index 3a861b568a..719e1fff7b 100644 --- a/target-i386/cpu.h +++ b/target-i386/cpu.h @@ -305,6 +305,7 @@ #define MSR_IA32_APICBASE_BASE (0xfffff<<12) #define MSR_IA32_FEATURE_CONTROL 0x0000003a #define MSR_TSC_ADJUST 0x0000003b +#define MSR_IA32_SPEC_CTRL 0x00000048 #define MSR_IA32_TSCDEADLINE 0x6e0 #define MSR_P6_PERFCTR0 0xc1 @@ -559,6 +560,9 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS]; #define CPUID_7_0_EBX_ADX (1U << 19) #define CPUID_7_0_EBX_SMAP (1U << 20) +#define CPUID_7_0_EDX_SPEC_CTRL (1U << 26) +#define CPUID_7_0_EDX_PRED_CMD (1U << 27) + #define CPUID_VENDOR_SZ 12 #define CPUID_VENDOR_INTEL_1 0x756e6547 /* "Genu" */ @@ -940,6 +944,7 @@ typedef struct CPUX86State { uint64_t xcr0; + uint64_t spec_ctrl; TPRAccess tpr_access_type; } CPUX86State; diff --git a/target-i386/kvm.c b/target-i386/kvm.c index 271b3b65ec..16ef197c5f 100644 --- a/target-i386/kvm.c +++ b/target-i386/kvm.c @@ -64,6 +64,7 @@ const KVMCapabilityInfo kvm_arch_required_capabilities[] = { static bool has_msr_star; static bool has_msr_hsave_pa; static bool has_msr_tsc_adjust; +static bool has_msr_spec_ctrl; static bool has_msr_tsc_deadline; static bool has_msr_feature_control; static bool has_msr_async_pf_en; @@ -787,6 +788,10 @@ static int kvm_get_supported_msrs(KVMState *s) has_msr_tsc_adjust = true; continue; } + if (kvm_msr_list->indices[i] == MSR_IA32_SPEC_CTRL) { + has_msr_spec_ctrl = true; + continue; + } if (kvm_msr_list->indices[i] == MSR_IA32_TSCDEADLINE) { has_msr_tsc_deadline = true; continue; @@ -1186,6 +1191,9 @@ static int kvm_put_msrs(X86CPU *cpu, int level) if (has_msr_bndcfgs) { kvm_msr_entry_set(&msrs[n++], MSR_IA32_BNDCFGS, env->msr_bndcfgs); } + if (has_msr_spec_ctrl) { + kvm_msr_entry_set(&msrs[n++], MSR_IA32_SPEC_CTRL, env->spec_ctrl); + } #ifdef TARGET_X86_64 if (lm_capable_kernel) { kvm_msr_entry_set(&msrs[n++], MSR_CSTAR, env->cstar); @@ -1524,6 +1532,9 @@ static int kvm_get_msrs(X86CPU *cpu) if (has_msr_bndcfgs) { msrs[n++].index = MSR_IA32_BNDCFGS; } + if (has_msr_spec_ctrl) { + msrs[n++].index = MSR_IA32_SPEC_CTRL; + } if (!env->tsc_valid) { msrs[n++].index = MSR_IA32_TSC; @@ -1671,6 +1682,9 @@ static int kvm_get_msrs(X86CPU *cpu) case MSR_IA32_BNDCFGS: env->msr_bndcfgs = msrs[i].data; break; + case MSR_IA32_SPEC_CTRL: + env->spec_ctrl = msrs[i].data; + break; default: if (msrs[i].index >= MSR_MC0_CTL && msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) { diff --git a/target-i386/machine.c b/target-i386/machine.c index 530d95dbc1..619cc98d87 100644 --- a/target-i386/machine.c +++ b/target-i386/machine.c @@ -613,6 +613,24 @@ static const VMStateDescription vmstate_msr_hyperv_time = { } }; +static bool spec_ctrl_needed(void *opaque) +{ + X86CPU *cpu = opaque; + CPUX86State *env = &cpu->env; + + return env->spec_ctrl != 0; +} + +static const VMStateDescription vmstate_spec_ctrl = { + .name = "cpu/spec_ctrl", + .version_id = 1, + .minimum_version_id = 1, + .fields = (VMStateField[]) { + VMSTATE_UINT64(env.spec_ctrl, X86CPU), + VMSTATE_END_OF_LIST() + } +}; + const VMStateDescription vmstate_x86_cpu = { .name = "cpu", .version_id = 12, @@ -756,6 +774,9 @@ const VMStateDescription vmstate_x86_cpu = { }, { .vmsd = &vmstate_msr_hyperv_time, .needed = hyperv_time_enable_needed, + }, { + .vmsd = &vmstate_spec_ctrl, + .needed = spec_ctrl_needed, } , { /* empty */ }
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