update to 1.95.4

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- update to 1.95.2:
  * Fixed the aggregation of the minimum ratio
  Intel:
  * [Airmont][Silvermont] Attempt to decode `tCKE` from DRMC
    register
  * [Airmont] Improve `tWTPr`, `B2B`, `tWWDR` timings
  * [Airmont] Provide a new IMC decoder
  * Add the Emerald Rapids architecture entry
  * [DDR5][DDR4] Add the `RCDw` IMC timing
  * [Raptor Lake ] De-activate the MSR Uncore counter
  AMD:
  * "Zen3/Barcelo-R" and "Zen3+ Rembrandt-R" codenames
  * [Zen] Thermal highest limit reset fix
  Misc:
  * Code review and Registers documentation:
    AMD HWCR, Intel HDC and DRP

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  * [Intel] RPL: voltage of Pcore, Ecore, System Agent
  * [Intel] RPL and ADL Chipset device IDs
  * [Intel] Decode the RPL IMC and improve DDR5 support
  * [Build] Raise `MAX_FREQ_HZ` up to 7125000000 Hertz
  * [Intel] Mobile {Coffee Lake, Kaby Lake} codenames
  * [Intel] Braswell codename detection
  * [AMD] SYSCFG Register
  * [AMD] EPYC 9654
  * [AMD] Transparent SME
  * [AMD] DRAM Data Scrambling
  * [AMD] Adding "Barcelo R" and "Rembrandt R"

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- update to 1.94.3:
  * [AMD][RMB] If UMC is quad channels then unpopulate odd channels
  * [AMD][RPL] Provide Service Processor Vcore as workaround
  * [UI] Auto size and lay performance capabilities window
  * [UI] Adding comments to the EEO and R2H technologies
  * [AMD][Raphael] 7950X3D, 7900X3D. support

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- update to 1.94.1:
  * [Intel] Gemini Lake
  * [AMD] Ryzen 5 6600 H SoC, UMC channels
  * [AMD] Rembrandt: maximum of two UMC channels
  * [AMD] Raphael: Decodes DIMM geometry from AddrCfg
  * [AMD] Zen: Aggregation refactored
  * [AMD] Improved DDR5 clock decoding
  * Optimized Idle Loop

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baserev update by copy to link target

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update to 1.93.1

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- update to 1.92.4:
  * [Intel/Skylake-X] Permits MSR_RING_PERF_LIMIT_REASONS

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- Repair deficient description grammar.

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update to version 1.92.3

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baserev update by copy to link target

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do not strip binaries

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Update to version 1.91.6

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baserev update by copy to link target

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